Transistors, in particular field-effect transistors such as MOS transistors, are employed in many integrated circuits. The noise of a MOS transistor limits the resolution of such a circuit. Noise is a limiting factor for the performance of a circuit particularly when said circuit has to process a signal having a very small amplitude or when a plurality of signals having a different bandwidth are to be processed simultaneously. Consequently, the performance particularly of analogue circuits is limited by the phenomenon of noise. In the course of scaling of CMOS technology in the range below 100 nanometers, noise influences increase continuously with each new technology generation.
A particular problem is posed by low-frequency noise (LF noise) which can be observed in MOS transistors. Low-frequency noise is caused by the random charging and discharging of defects to the interface between the transistor channel and the gate dielectric. At low frequencies, this mechanism supplies the dominant noise contribution. The corresponding defects are also called interface states on account of their spatial position.
It is known from Brederlow, R et al. (1998) “Influence of fluorinated gate oxides on low-frequency noise of MOS transistors under analog operation”, In: Proceedings of the 28th European Solid State Device Research Conference, pp. 472-475, that the noise contributions of individual defects can be detected metrologically particularly in the case of very small transistors.
Since low-frequency noise is grounded in the physics of the components used or is linked to the quality of the interface between the channel region and the gate insulating layer by way of the so-called interface state density, it is attempted in accordance with the prior art to improve low-frequency noise properties essentially by means of optimizing the fabrication process. However, narrow limits are imposed on such technological optimization possibilities. Examples of improving the fabrication process in order to suppress low-frequency noise are disclosed in Brederlow, R et al. (1999) “Fluctuations in the Low Frequency Noise of MOS transistors and their Modeling in analog and RF-Circuits”, IEDM 1999 Tech. Dig., pp. 159-162.
Another approach known from the prior art for suppressing low-frequency noise consists in positioning or choosing the operating point of the transistors such that the noise is reduced or even minimized. It is known, for example, that the choice of the operating point in the context of analogue circuitry (suitable operating points therein are typically Vg−Vt=100 mV to 500 mV, where Vd>Vg−Vt, where Vg is the gate voltage, Vt is the threshold voltage and Vd is the drain voltage of the transistor) permits a noise minimum to be achieved, see e.g. Christensen, S et al. (1968) “Low frequency noise in MOS transistors—I theory”, Solid-St. El. 11, pp. 791-812. What is disadvantageous about this concept is the limitation of the degrees of freedom in the circuit designed from a different standpoint e.g. with regard to the power consumption, the driving range, the bandwidth, etc. Furthermore, the gain in performance that can be obtained with the adjustment of the operating point of the transistor is small.
Since the low-frequency noise voltages or noise currents of a MOS transistor are inversely proportional to the root of the active area thereof (see e.g. Christensen, S et al.), there is the possibility of reducing the low-frequency noise of a circuit by choosing the component areas to be large. However, one disadvantage of this method results from the increased area taken up, but it may also result from an increased power consumption. This last necessarily results if the bandwidth of the circuit cannot be reduced, since then the widths but not the lengths of the transistors can be increased. The current consumption in the circuit with regard to the paths in which the relevant transistors are operated rises approximately proportionally to the width of the relevant transistors. Furthermore, all capacitive loads brought about by a given circuit rise, such, in particular, the input capacitance of sensitive amplifier circuits. A higher AC power loss also occurs for this reason.
DE 101 17 362 A1 discloses a random number generator having a semiconductor component having at least one electrically active defect in the structure of the semiconductor component, having an occupation detection unit, which is coupled to the semiconductor component and which is set up in such a way that an occupation or a change of the occupation in the electrically active defect can be ascertained, and having a random number conversion unit, which is coupled to the occupation detection unit and which is set up in such a way that a random number is formed from the ascertained occupation or the ascertained change of the occupation in the electrically active defect.